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? semiconductor components industries, llc, 2001 march, 2001 rev. 3 1 publication order number: cs8151c/d cs8151c 5.0 v, 100 ma low dropout linear regulator with watchdog, reset , and wake up the cs8151c is a precision 5.0 v, 100 ma micropower voltage regulator with very low quiescent current (400 m a typical at 200 m a load). the 5.0 v output is accurate within 1.0% and supplies 100 ma of load current with a typical dropout voltage of 400 mv. microprocessor control logic includes watchdog, wake up and reset . this unique combination of low quiescent current and full microprocessor control makes the cs8151c ideal for use in battery operated, microprocessor controlled equipment. the cs8151c wake up function brings the microprocessor out of sleep mode. the microprocessor in turn, signals its wake up status back to the cs8151c by issuing a watchdog signal. the watchdog logic function monitors an input signal (wdi) from the microprocessor. the cs8151c responds to the falling edge of the watchdog signal which it expects at least once during each wakeup period. when the correct watchdog signal is received, a falling edge is issued on the wakeup signal line. reset is independent of v in and operates correctly to an output voltage as low as 1.0 v. a reset signal is issued in any of three situations. during power up the reset is held low until the output voltage is in regulation. during operation if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. and finally, a reset signal is issued if the regulator does not receive a watchdog signal within the wake up period. the reset pulse width, wake up signal frequency, and wake up delay time are all set by one external capacitor c delay . the regulator is protected against short circuit, over voltage, and thermal runaway conditions. the device can withstand 74 volt peak transients, making it suitable for use in automotive environments. features ? 5.0 v 1.0%/100 ma output voltage ? micropower compatible control functions wake up watchdog reset ? low dropout voltage: 400 mv @ 100 ma ? low sleep mode quiescent current (400 m a typ) ? protection features thermal shutdown short circuit 74 v peak transient capability reverse transient (50 v) http://onsemi.com dip8 n suffix case 626 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 8 pin connections and marking diagram 1 8 cs8151c awl yyww v out gnd nc delay v in wdi wake up reset device package shipping ordering information cs8151cgn8 dip8 50 units/rail
cs8151c http://onsemi.com 2 figure 1. block diagram v in delay wdi reset v out wake up sense gnd overvoltage shutdown current source (circuit bias) current limit sense wake up circuit + timing circuit watchdog circuit thermal shutdown falling edge detector bandgap reference reset circuit error amplifier v out v out
cs8151c http://onsemi.com 3 absolute maximum ratings* rating value unit power dissipation internally limited output current (v out , reset , wake up) internally limited reverse battery 15 v peak transient voltage (60 v load dump @ v in = 14 v) +74 v maximum negative transient (t < 2.0 ms) 50 v esd susceptibility (human body model) 2.0 kv esd susceptibility (machine model) 200 v logic inputs/outputs 0.3 to +6.0 v storage temperature range 55 to +150 c lead temperature soldering wave solder (through hole styles only) note 1. 260 peak c 1. 10 seconds max. *the maximum package power dissipation must be observed. electrical characteristics (0 c t a 70 c, 0 c t j 125 c, 6.0 v v in 26 v, 100 m a i out 100 ma, c2 = 47 m f (esr < 8.0 w ), c delay = 0.1 m f; unless otherwise specified.) characteristic test conditions min typ max unit output section output voltage, v out 9.0 v < v in < 16 v 6.0 v < v in < 26 v, 0 < i out < 100 ma 4.95 4.90 5.0 5.0 5.05 5.10 v v dropout voltage (v in v out ) i out = 100 ma i out = 100 m a 400 100 600 150 mv mv load regulation v in = 14 v, 100 m a < i out < 100 ma 10 50 mv line regulation i out = 1.0 ma, 6.0 v < v in < 26 v 10 50 mv ripple rejection 7.0 v < v in < 17 v @ f = 120 hz, i out = 100 ma 60 75 db current limit v out = 4.5 v 100 250 ma thermal shutdown 150 180 210 c overvoltage shutdown v out < 1.0 v 50 56 62 v quiescent current i out = 200 m a (sleep) i out = 50 ma i out = 100 ma (wake up) 0.4 4.0 12 0.75 20 ma ma ma reverse current v out = 5.0 v, v in = 0 v 1.0 1.5 ma reset threshold high (rth) rth v out increasing v out 0.3 v out 0.04 v threshold low (rtl) rtl v out decreasing 4.5 4.7 4.91 v hysteresis rth rtl 150 200 250 mv output low 1.0 v < v out rtl, i out = 25 m a 0.2 0.8 v output high i out = 25 m a, v out > rth 3.8 4.2 5.1 v current limit reset = 0 v, v out > v rth (sourcing) reset = 5.0 v, v out > 1.0 v (sinking) 0.025 0.1 0.5 12 1.30 80 ma ma delay time por mode 3.0 5.0 7.0 ms
cs8151c http://onsemi.com 4 electrical characteristics (continued) (0 c t a 70 c, 0 c t j 125 c, 6.0 v v in 26 v, 100 m a i out 100 ma, c2 = 47 m f (esr < 8.0 w ), c delay = 0.1 m f; unless otherwise specified.) characteristic unit max typ min test conditions watchdog input threshold high 1.4 2.0 v threshold low 0.8 1.3 v hysteresis 25 100 mv input current 0 < wdi < 6.0 v 10 0 +10 m a pulse width 50% wdi falling edge to 50% wdi rising edge and 50% wdi rising edge to 50% wdi falling edge (see figures 2, 3, and 4) 5.0 m s wake up output wake up period see figure 2. 30 40 50 ms wake up duty cycle nominal see figure 4. 40 50 60 % reset high to wake up rising delay time 50% reset rising edge to 50% wake up edge (see figures 2, 3, and 4) 15 20 25 ms wake up response to watchdog input 50% wdi falling edge to 50% wake up falling edge 2.0 10 m s wake up response to reset 50% reset falling edge to 50% wake up falling edge, v out = 5.0 v 4.5 v 2.0 10 m s output low i out = 25 m a (sinking) 0.2 0.8 v output high i out = 25 m a (sourcing) 3.8 4.2 5.1 v current limit wake up = 5.0 v wake up = 0 v 0.025 0.5 1.0 7.0 3.5 ma ma package pin description package pin # dip8 pin symbol function 1 v in supply voltage to the ic. 2 wdi cmos/ttl compatible input lead. the watchdog function monitors the falling edge of the incoming signal. 3 wake up cmos/ttl compatible output consisting of a continuously generated signal used to wake up the microprocessor from sleep mode. 4 reset cmos/ttl compatible output lead reset goes low whenever v out drops by more than 6.0% from nominal, or during the absence of a correct watchdog signal. 5 delay input lead from timing capacitor for reset and wake up signal. 6 nc no connection. 7 gnd ground connection. 8 v out regulated output voltage 5.0 v 2%.
cs8151c http://onsemi.com 5 timing diagrams watchdog pulse width v in reset wake up wdi v out wake up duty cycle = 50% power up sleep mode normal operation with varying watchdog signal reset high to wake up delay time por figure 2. power up, sleep mode and normal operation figure 3. error condition: watchdog remains low and a reset is issued v in reset wake up wdi v out por reset high to wake up delay time reset delay time reset high to wake up delay time wake up period por reset wake up wdi v out watchdog pulse width rtl por power down wake up period figure 4. power down and restart sequence
cs8151c http://onsemi.com 6 definition of terms dropout voltage: the inputoutput voltage differential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100mv from the nominal value obtained at 14v input, dropout voltage is dependent upon load current and junction temperature. input voltage: the dc voltage applied to the input terminals with respect to ground. line regulation: the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation: the change in output voltage for a change in load current at constant chip temperature. quiescent curr ent: the part of the positive input current that does not contribute to the positive load current. the regulator ground lead current. ripple rejection: the ratio of the peaktopeak input ripple voltage to the peaktopeak output ripple voltage. current limit: peak current that can be delivered to the output. circuit description functional description to reduce the drain on the battery a system can go into a low current consumption mode when ever its not performing a main routine. the wake up signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. the nominal output is a 5.0 volt square wave with a duty cycle of 50% at a frequency that is determined by a timing capacitor, c delay . when the microprocessor receives a rising edge from the wake up output, it must issue a watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode. figure 5. wake up response to wdi wake up response to wdi wake up wdi figure 6. wake up response to reset (low voltage) wake up response to reset reset wake up the first falling edge of the watchdog signal causes the wake up to go low within 2.0 m s (typ) and remain low until the next wake up cycle (see figure 5). other watchdog pulses received within the same cycle are ignored (figures 2, 3, and 4). during power up, reset is held low until the output voltage is in regulation. during operation, if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. after the reset delay, reset returns high. the watchdog circuitry continuously monitors the input watchdog signal (wdi) from the microprocessor. the absence of a falling edge on the watchdog input during one wake up cycle will cause a reset pulse to occur at the end of the wake up cycle (see figure 3). the wake up output is pulled low during a reset regardless of the cause of the reset . after the reset returns high, the wake up cycle begins again (see figure 3). the reset pulse width, wake up signal frequency and reset high to wake up delay time are all set by one external capacitor c delay . wake up period = (4 10 5 )c delay reset delay time = (5 10 4 )c delay reset high to wake up delay time = (2 10 5 )c delay capacitor temperature coefficient and tolerance as well as the tolerance of the cs8151c must be taken into account in order to get the correct system tolerance for each parameter.
cs8151c http://onsemi.com 7 application notes output stage protection the output stage is protected against overvoltage, short circuit and thermal runaway conditions (see figure 7). if the input voltage rises above the overvoltage shutdown threshold (e.g. load dump), the output shuts down. this response protects the internal circuitry and enables the ic to survive unexpected voltage transients. should the junction temperature of the power device exceed 180 c (typ) the power transistor is turned off. thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the ic. figure 7. typical circuit waveforms for output stage protection v in v out i out > 50 v load dump short circuit thermal shutdown stability considerations the output or compensation capacitor c2 (see figure 8) helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. figure 8. test and application circuit showing output compensation cs8151c v in c1* 0.1 m f v out reset c2** 10 m f *c1 required if regulator is located far from the power supply filter. **c2 required for stability. r rst the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provide this information. the value for the output capacitor c2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. to determine an acceptable value for c2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator
cs8151c http://onsemi.com 8 performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 9) is: p d(max) ( v in(max) v out(min) ) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? i q control features i out i in figure 9. single output regulator with key performance parameters labeled v in v out } a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. heat sinks each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja : r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. figure 10. application diagram v in c delay v out wdi reset gnd cs8151c microprocessor wake up c delay c1 c2 v cc i/o reset i/o battery
cs8151c http://onsemi.com 9 package dimensions dip8 n suffix case 62605 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 package thermal data parameter dip8 unit r q jc typical 52 c/w r q ja typical 100 c/w
cs8151c http://onsemi.com 10 notes
cs8151c http://onsemi.com 11 notes
cs8151c http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8151c/d smart regulator is a registered trademark of semiconductor components industries, llc. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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